1. Field of the Invention
The present invention generally relates to a phase detector, and more particularly, to a phase detector for a half-rate bang-bang clock and data recovery (CDR) circuit.
2. Description of Related Art
Because of the popularization and development of the communication technology, data are now transmitted with a higher bit rate than ever before. However, when operating with a very high transmitting bit rate, e.g., 5 GHz, it is a serious challenge to design an oscillator adapted for an adjustment range thereof with a reasonable jitter condition. Accordingly, a half-rate CDR technology is developed in response to such a challenge. According to the half-rate CDR technology, when tracking a data signal, a voltage control oscillator (VCO) is required to generate a clock signal which frequency is equal to a half of a bit rate of the data transmitted thereby.
In a thesis, “A 9-16 Gb/s Clock and Data Recovery Circuit with Three-state Phase Detector and Dual-path Loop Architecture”, published in European Solid-State Circuits Conference (ESSCIRC) 2003, A. Rezayee and K. Martin propose a phase detector for a half-rate bang-bang CDR circuit, as shown in FIG. 1. The phase detector includes four D flip-flops 101 through 104, four exclusive OR gates (XOR gates) 111 through 114, and two multiplexer MUX1 and MUX2. A VCO (not shown in FIG. 1) provides four clock signals CK0, CK90, CK180, and CK270, in which CK0 and CK90 are orthogonal signals, while CK180 and CK270 are also orthogonal signals. CK180 is a phase-reversed CK0, and CK270 is a phase-reversed CK90. The D flip-flops 101 through 104 sample data signal DATA respectively with the aforementioned four clock signals, so as to provide consecutive sampling values D0, D90, D180, and D270. The XOR gates 111 through 114 provide comparison values UP1, DN1, UP2 and DN2, according to a comparison result between each of the sampling values and the next sampling value. Finally, the multiplexers MUX1 and MUX2 respectively output two of the above four comparison values according to high or low statuses of the clock signals CK0 and CK90, as instruction signals UP and DN.
The phases of the clock signals CK0, CK90 and phase-reversed CK0 and CK90 quartered 360° of each duty cycle. The D flip-flops 101 through 104 respectively sample the data signal DATA for four times in each of the clock duty cycle. The XOR gates 111 through 114 compare the foregoing consecutive sampling values, and determine the clock signal being behind or before the data signal DATA according to the comparison result. The comparison values UP1 and UP2 are alternately output as the instruction signal UP, while the comparison values DN1 and DN2 are alternately output as the instruction signal DN. When the instruction signal UP is at a logic high level, the VCO increases the frequency of the clock signals CK0 and CK90. When the instruction signal DN is at a logic high level, the VCO decreases the frequency of the clock signals CK0 and CK90.
Because of the employment of clock signals of different phases for consecutively sampling the data signals, the phase detector of FIG. 1 is able to track full-rate data signals with a half-rate clock signal. The approach of determining the clock signal being behind or before the data signal by comparing consecutive sampling values is exactly a characteristic of a bang-bang CDR circuit. FIG. 2 is a clock sequence example of the phase detector of FIG. 1 showing the situation in which the clock signal is dropped behind for reference.
The phase detector of FIG. 1 adopts a completely symmetric design, in which loads driven by signals are symmetric, and transmission path of the signals are also symmetric. However, when operating with a very high transmitting bit rate, if a sum of a clock to output delay time (CK-Q delay) of the D flip-flops 101 through 104 and a delay time of the XOR gates 111 through 114 exceeds T/4, in which T is the duty cycle of the clock signals CK0 and CK90, there will generate an unpredicted glitch in the instruction signals UP and DN, as shown in FIG. 3. The fine line section in FIG. 3 is an undelayed ideal signal waveform, while the thick line section in FIG. 3 is a signal waveform describing the above-mentioned situation that the sum of the clock to output delay times of the D flip-flops 101 through 104 and the XOR gates 111 through 114 exceeds T/4. Delayed comparison values UP1, DN1, UP2, and DN2 will cause a glitch of the instruction signal DN, as shown as numeral 301 of FIG. 3. This glitch is undesired, because it often causes ripples generated with a control voltage of the VCO, and therefore causes glitters of the frequency and phase of outputted clock signals.